library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu2 is
port(a:in std_logic_vector(3 downto 0);
	 b:in std_logic_vector(3 downto 0);
	 Cin: in std_logic;
	 sel: in std_logic_vector(1 downto 0);
	 m: in std_logic;
	 Cout:out std_logic;
	 r:out std_logic_vector(3 downto 0));

end alu2;

architecture bhv of alu2 is
signal logic:std_logic_vector(4 downto 0);
signal arit:std_logic_vector(4 downto 0);
signal t_result:std_logic_vector(4 downto 0);
signal t_a:std_logic_vector(4 downto 0);
signal t_b:std_logic_vector(4 downto 0);


begin

t_a<='0'&a;
t_b<='0'&b;

with sel(1 downto 0) select
logic <= (not t_a) when "00",
		t_a and t_b when "01",
		t_a or t_b when "10",
		t_a xor t_b when "11",
		"-----" when others;
		
with sel(1 downto 0) select
arit <= Cin + t_a + t_b when "00",
		 Cin + t_a - t_b when "01",
		 Cin + t_b - t_a when "10",
		 (not b) & '0' when "11",
		 "-----" when others;

with m select
r<=arit(3 downto 0) when '1',
	logic(3 downto 0) when '0',
	"----" when  others;

with m select
Cout<=arit(4) when '1',
	logic(4) when '0',
	'-' when  others;


end bhv;
